1. Field of the Invention
The present invention relates to semiconductor memory devices. In particular, the present invention relates to a structure for implementing reduction in a test time of a semiconductor memory device and improvement of reliability of the test. More particularly, the present invention relates to a structure of a semiconductor memory device having a plurality of input/output pins enabling, by writing and reading data through a specific input/output pin, simultaneous input/output of data to the other input/output pins, in a test mode operation.
2. Description of the Background Art
With increase of a storage capacity of a semiconductor memory device and complication of its circuit structure, a chip having a latent defective factor which has been generated during its manufacturing process inevitably exists at a certain frequency immediately before shipment of the semiconductor memory device.
More specifically, there may be a latent defective factor of an MOS transistor which is a component of the semiconductor memory device, such as a defective gate insulating film, a defective interlayer insulating film between interconnections, a broken interconnection, a leakage current between interconnections, and a defect caused by a particle mixed during the manufacturing process. Shipment of such a semiconductor memory device having a latent defective factor as a product causes generation of a failure in a so-called "initial failure mode."
Therefore, screening is generally carried out by a so-called "burn-in" test in which a semiconductor memory device is operated under a high temperature and high pressure to reveal the initial defect and to eliminate the defective product before shipment. However, time required for the "burn-in" test becomes longer in proportion to a memory capacity even in a simple write/read cycle. Increase in the test time directly connects to increase in the chip cost.
In order to suppress increase in the test time, a structure is employed in which a plurality of semiconductor memory devices are arranged on a test board to test a number of semiconductor memory devices in parallel.
However, with a semiconductor memory device made far larger in capacity in recent years, the number of data input/output pins has increased. As a result, the number of semiconductor memory devices which can be tested simultaneously with one tester decreases. The test time is increased even if semiconductor memory devices are tested in parallel as described above, which in turn increases the test cost.
In order to prevent increase in the test cost, a multi-bit test is proposed. More specifically, by structuring a semiconductor memory device so as to carry out comparison and matching detection among a plurality of read data therein to output a signal indicating the result to a specific input/output terminal, the number of input/output terminals when seen from the side of the tester is apparently reduced in a test mode operation. By employing such a structure, it becomes possible to suppress decrease of the number of semiconductor memory devices which can be measured simultaneously by one tester.
FIG. 18 is a schematic block diagram showing a structure of a conventional semiconductor memory device capable of the above described multi-bit test operation.
In a reading operation in a normal operation mode, in response to external address signals A0 to Ai applied through an address signal input terminal 8, storage data of a specific memory cell selected from a memory cell array 15 is amplified by sense amplifiers 14 and 16 to be output to internal data buses by I/O circuits 14 and 16 as internal read data q0 to q3. Input/output buffer circuits 61 to 64 include switch circuits 91 to 94 switching a connection state with external input/output terminals 65 to 68 between the following two connection states. In response to a test mode specify signal TE generated by a control signal generating circuit 11, switch circuits 91 to 94 connect input/output buffer circuits 61 to 64 and input/output terminals 65 to 68 individually in the normal operation mode. More specifically, in FIG. 18, switch circuits 91 to 94 are connected in a state as indicated by the solid line.
Therefore, input/output buffer circuits 61 to 64 receive internal read data q0 to q3 read out from four memory cells, generate external read data DQ0 to DQ3, and output the data to data input/output terminals 65 to 68 individually.
In a writing operation in the normal operation mode, input/output buffer circuits 61 to 64 receive external write data DQ0 to DQ3 applied to external input/output terminals 65 to 68 to output the data individually to four memory cells selected by external address signals A0 to Ai through I/O circuits 14 and 16, oppositely in the above reading operation.
On the other hand, in response to a write enable signal EXT.W, an output enable signal EXT.OE, a row address strobe signal EXT.RAS, and a column address strobe signal EXT.CAS which are external control signals, and specific external address signals, for example, A0 and A1, of external address signals A0 to Ai, control signal generating circuit 11 detects that a test mode (for example, burn-in mode) was specified, and outputs an active test mode specify signal TE.
In response to test mode specify signal TE, switch circuits 90 to 94 connect input/output buffer circuits 61 to 64 together with a specific input/output terminal, for example, input/output terminal 65. More specifically, in FIG. 18, switch circuits 91 to 94 are connected in a state as indicated by the dotted line.
Therefore, in the writing operation in the test mode, write data applied to input/output terminal 65 is output in common to four memory cells selected by external address signals A0 to Ai through I/O circuits 14 and 16.
In the reading operation in the test mode, internal read signals q0 to q3 from four memory cells selected by external address signals A0 to Ai are applied to a logic synthesizing circuit 47. Logic synthesizing circuit 47 determines whether these signals match or mismatch. According to the determination result, logic synthesizing circuit 47 outputs a determination signal TMq0 to input/output terminal 65.
Therefore, in the test mode operation, data is input/output only through input/output terminal 65. More specifically, a semiconductor memory device in a x4 configuration can be tested as one in a x1 configuration in the normal operation. Therefore, even if the number of data input/output pins is increased in a semiconductor memory device, the number of semiconductor memory devices which can be simultaneously tested in parallel with one tester is not decreased.
The semiconductor memory device having the conventional data bit compression function is structured so that data from a specific input/output terminal is written in a plurality of memory cells in common. This structure rises the following problem.
FIG. 19 is a circuit diagram showing one example of a structure of a portion corresponding to memory cell array 15 and sense amplifier+I/O circuits 14 and 16 of a semiconductor memory device 201 capable of the multi-bit test operation.
Referring to FIG. 19, sense amplifiers 20, 22, and 24 are arranged opposite to sense amplifiers 21, 23, and 25 with bit line pairs therebetween. Respective bit lines are connected to the opposing sense amplifiers alternately. More specifically, a bit line ZBL10 of paired bit lines BL10 and ZBL10 connected to sense amplifier 21 is arranged between paired bit lines BL00 and ZBL00 connected to sense amplifier 20, for example.
Paired bit lines BL00 and ZBL00 are connected to internal data buses IO0 and ZIO0 through N channel MOS transistors 26a and 26b, respectively. Similarly, paired bit lines BL10 and ZBL10, BL20 and ZBL20, and BL30 and ZBL30 are connected to internal data buses IO1 and ZIO1, IO2 and ZIO2, and IO3 and ZIO3 through N channel MOS transistors 26c and 26d, 26e and 26f, and 26g and 26h, respectively.
The gate potentials of N channel MOS transistors 26a to 26h are controlled by the same column select signal CSL0.
Sense amplifier 20 is connected to bit line pair BL00, ZBL00, and according to power supply potential supplied from sense amplifier control lines S2N and S2B, amplifies the potential difference between the paired bit lines. Sense amplifiers 21, 22, and 23 connected to bit line pairs BL10, ZBL10, BL20, ZBL20, and BL30, ZBL30 similarly amplify the potential differences between the paired bit lines to which they are connected.
Internal data buses IO0 and ZIO0 are connected to input/output buffer circuit 61 to transmit internal read signal q0. Similarly, internal data buses IO1 and ZIO1, IO2 and ZIO2, and IO3 And ZIO3 are connected to input/output buffer circuits 62, 63, and 64, respectively, to transmit internal read signals q1, q2, and q3.
Memory cells 28a, 28b, 28c, and 28d are connected to crossing points between a word line WL0 and bit lines BL00, BL10, BL20, and BL30, respectively.
In the writing operation in the normal operation mode, external write data DQ0 to DQ3 applied from external terminals 65 to 68 are converted to complementary internal write signals corresponding thereto in input/output buffer circuits 61 to 64 to be transmitted to internal data buses IO0 and ZIO0 to IO3 and ZIO3. When word line WL0, for example, is selected in response to external address signals A0 to Ai, and internal data buses IO 0 and ZIO0 to IO3 and ZIO3 are connected to respective corresponding bit line pairs in response to column select signal CSL0, storage data corresponding to data applied to external input/output terminals 65 to 68 are to be individually written in memory cells 28a to 28d.
On the other hand, in the writing operation in a multi-bit test mode, a complementary signal according to data DQ0 applied to external input/output terminal 65, for example, is transmitted to all internal data buses IO0 and ZIO0 to IO3 and ZIO3 in common. If this write data is at a logical low or L level, for example, when data is written in memory cells 28a to 28d selected by word line WL0 and column select signal CSL0, bit lines BL00 to BL30 connected to these memory cells all attain the L level. On the other hand, bit lines ZBL00 to ZBL30 paired with these bit lines attain a logic high or H level.
In FIG. 19, a bit line potential arrangement is shown in the case where a signal at the L level is written in memory cells 28a to 28d, as described above. Since the bit line pairs are arranged alternately, the adjacent bit lines, for example, BL00 and BL10 are both at the L level, and bit lines ZBL00 and ZBL10 are both at the H level.
When data is written in a multi-bit test operation as described above in a burn-in test mode, the following problem occurs. More specifically, in the burn-in test, it is necessary to reveal a latent leakage current between bit lines or the like, for example. However, if data is written in bit line pairs arranged as described above in the multi-bit test operation, the adjacent bit lines have the same potential, causing no voltage stress applied between these bit lines. Therefore, a latent defect between these adjacent bit lines cannot be detected in the burn-in test, decreasing the reliability of the burn-in test conducted before shipment.